A dynamic quality-adjustable H.264 intra coder

Author

Jia-Wei Chen ; Hsiu-Cheng Chang ; Jinn-Shyan Wang ; Jiun-In Guo

Author_Institution

Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan

Volume

57

Issue

3

fYear

2011

fDate

8/1/2011 12:00:00 AM

Firstpage

1203

Lastpage

1211

Abstract

This paper presents a flexible qualityadjustable H.264 intra frame encoder for power aware video applications. Encapsulating a reconfigurable algorithm, the proposed design can configure the encoding search algorithm to operate at different quality modes with the design tradeoff between video quality and power consumption. In addition, some timing optimization schemes are proposed to increase the hardware throughput of the proposed design to encode H.264 intra video sequences on D1, HD720 and HD1080 with 10 mW to 16 mW, 27 mW to 45 mW, and 60 mW power consumption under different quality modes, respectively. Implemented by using a 90nm CMOS technology, the proposed design comprises 91 kgates and 2.9 kB internal memory.

Keywords

CMOS integrated circuits; power consumption; search problems; video codecs; video coding; CMOS technology; H.264 intra video sequences; dynamic quality-adjustable H.264 intra coder; flexible quality- adjustable H.264; power 10 nW; power 16 mW; power 27 mW; power 45 mW; power 90 mW; power consumption; search algorithm; video quality; Algorithm design and analysis; Clustering algorithms; Encoding; Hardware; Heuristic algorithms; Prediction algorithms; Streaming media; H.264 Intra Frame Coder; Quality-Adjustable Encoding; VLSI Architecture; Video Encoding;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/TCE.2011.6018875

Filename

6018875