Title :
A data-path multiplier with automatic insertion of pipeline stages
Author :
Asato, Creigton ; Ditzen, Christoph ; Dholakia, Suresh
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
fDate :
4/1/1990 12:00:00 AM
Abstract :
The architecture of an easy-to-use, highly configurable, compiled pipelined multiplier is described. The multiplier is designed for use in high-performance pipelined data paths such as those found in digital signal processing applications. The multiplier compiler allows the data-path designer to control the bit width of the multiplier as well as the clock-cycle time, setup time, and output-delay time. Given these parameters, the multiplier compiler uses a simple timing model to decide where pipeline stages should be inserted into the multiplier and generates a pipelined multiplier that meets the designer´s system requirements
Keywords :
VLSI; circuit layout CAD; digital arithmetic; multiplying circuits; pipeline processing; VLSI; automatic insertion of pipeline stages; bit width; clock-cycle time; compiled pipelined multiplier; configurable multiplier; data-path multiplier; digital signal processing; high-performance pipelined data paths; multiplier compiler; output-delay time; setup time; timing model; CMOS technology; Circuits; Clocks; Delay effects; Digital signal processing; Pipeline processing; Signal design; Throughput; Timing; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of