Title :
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver
Author :
Bächtold, Martin ; Spasojevic, Mirko ; Lage, Christian ; Ljung, Per B.
Author_Institution :
Coyote Syst. Inc., San Francisco, CA, USA
fDate :
3/1/2000 12:00:00 AM
Abstract :
As integrated circuit (IC) manufacturing technology pushes toward the deep submicron (DSM) regime, the interconnect behavior begins to dominate the overall chip performance. Traditional interconnect characterization methods do not offer the required accuracy or the versatility to tackle challenges of DSM design. We present a system for interconnect parasitic capacitance extraction using an extremely fast three-dimensional (3-D) solver, capable of handling general geometry configurations and providing high accuracy. The contributions in this work make 3-D field solvers an attractive and, for the first time, computationally feasible approach to calculating interconnect parasitics. The system represents a significant performance leap in 3-D interconnect characterization, making it well suited for full-chip extraction and for high-accuracy characterization of critical nets, block IP, and standard and custom cell designs
Keywords :
ULSI; capacitance; circuit layout CAD; electronic engineering computing; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; partial differential equations; 3D interconnect characterization; ULSI interconnects; block IP designs; critical net parasitic extraction; custom cell designs; deep submicron regime; fast 3D field solver; full-chip extraction; general geometry configurations; high-accuracy characterization; interconnect behavior; interconnect parasitic capacitance extraction; interconnect parasitics; standard cell designs; three-dimensional solver; Computational geometry; Electrostatics; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit manufacture; Integrated circuit technology; Libraries; Parasitic capacitance; Pattern matching; Ultra large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on