Yield prediction by sampling IC layout

Author

Allan, Gerard A.

Author_Institution

Dept. of Electron. & Electr. Eng., Edinburgh Univ., UK

Volume

19

Issue

3

fYear

2000

fDate

3/1/2000 12:00:00 AM

Firstpage

359

Lastpage

371

Abstract

This paper reports a survey sampling-based methodology for critical area and other property estimates of IC layout. A software implementation of the method, Edinburgh yield estimator sampling (EYES) is presented. The EYES tool implements the survey sampling-based methodology for critical area estimation enabling the yield prediction of ULSI chips. The method requires an analysis of only a small fraction of the chip layout. As a result the practical application of the technique is not limited by the size of the chip, or the design hierarchy. The EYES system is able to process non-Manhattan layout. This enables yield predictions in a reasonable time for even the largest state-of-the-art chips, using modest computing resources

Keywords

ULSI; VLSI; circuit layout CAD; integrated circuit layout; integrated circuit modelling; integrated circuit yield; EYES tool; Edinburgh yield estimator sampling; IC layout; ULSI chips; critical area estimation; nonManhattan layout; property estimates; software implementation; survey sampling-based methodology; yield prediction; Algorithm design and analysis; Application software; Application specific integrated circuits; Data mining; Eyes; Geometry; Integrated circuit layout; Sampling methods; Ultra large scale integration; Yield estimation;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.833204

Filename

833204