A 3.8-ns CMOS 16×16-b multiplier using complementary pass-transistor logic

Author

Yano, Kazuo ; Yamanaka, Toshiaki ; Nishida, Takashi ; Saito, Masayoshi ; Shimohigashi, Katsuhiro ; Shimizu, Akihiro

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

25

Issue

2

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

388

Lastpage

395

Abstract

A 3.8-ns, 257-mW, 16×16-b CMOS multiplier with a supply voltage of 4 V is described. A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality. Its multiplication time is the fastest ever reported, even for bipolar and GaAs ICs, and it can be enhanced further to 2.6 ns with 60 mW at 77 K

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated logic circuits; multiplying circuits; 16 bit; 16×16-b multiplier; 2.6 ns; 257 mW; 3.8 ns; 4 V; 60 mW; 77 K; CMOS multiplier; CMOS output inverters; CPL; VLSI; complementary pass-transistor logic; fast multipliers; high logic functionality; lower input capacitance; multiplication time; nMOS pass-transistor logic network; supply voltage; CMOS logic circuits; CMOS technology; Capacitance; Josephson junctions; Latches; Logic circuits; Logic devices; MOS devices; Pulse inverters; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.52161

Filename

52161