Compensating for moderate effective throughput at the desktop

This article presents the design and development of a networking system architecture targeted to support high-speed TCP/IP communication over ATM. The discussed architecture has been developed in the form of an integrated system which incorporates state-of-the-art software and hardware subsystems, and an OC-12c ATM adapter (622 Mb/s). Moreover, the design of this embedded system has been based on the Chorus real-time operating system, which, in turn, hosts an accelerated TCP/IP protocol stack over ATM. Furthermore, the embedded system board has been developed according to the PCI specification to easily be plugged into a host platform. In addition, the OC-12c ATM adapter subsystem has been designed and developed in order to also be plugged into the same host. The developed architecture has proven very efficient and reliable, providing high-throughput and low-latency bulk data communications. The measured performance on an OC-3c-based (155 Mb/s) testbed has shown that an optimally implemented TCP/IP stack, hosted by a real-time kernel and coupled with an ATM adapter, offers a robust desktop platform for high-speed end-to-end communications. The main feature of the accelerated TCP/IP protocol stack is the out-of-band processing of control and data information. The protocol accelerator embedded system processes the TCP/IP headers and accomplishes checksum computations, while data is transferred from the host´s user memory space directly to the network. Finally, for validation purposes, the prototype system has been incorporated in an existing networking infrastructure targeted to support mass storage applications