Title :
The SDC cell-A novel design methodology for high-speed arithmetic modules using CMOS/BiCMOS precharged circuits
Author :
Hayashi, Takehisa ; Doi, Toshio ; Asai, Mitsuo ; Ishibashi, Ken Ichi ; Shukuri, Shoji ; Watanabe, Atsuo ; Suzuki, Makoto
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
4/1/1990 12:00:00 AM
Abstract :
The shielded dynamic complex-gate (SDC) cell is a cell-based design methodology for generating high-speed modules or macrocells using precharged circuit technology. In order to achieve ultrafast operation, a BiCMOS precharged circuit has been developed. This circuit is about 1.5 to 2.0 times faster than the conventional CMOS precharged circuit. The effect of alpha-particle injection under low-voltage operation has been studied, and CMOS/BiCMOS precharged circuits with alpha-particle-induced noise suppression have been proposed. A 32-b arithmetic and logic unit (ALU) utilizing a BiCMOS SDC cell designed and fabricated with 0.5-μm BiCMOS technology is discussed. The application of the SDC cell design to a mainframe execution unit (parallel adder) is also described
Keywords :
BIMOS integrated circuits; CMOS integrated circuits; VLSI; digital arithmetic; integrated circuit technology; integrated logic circuits; 0.5 micron; 32 bit; ALU; BiCMOS SDC cell; BiCMOS precharged circuit; BiCMOS technology; CMOS precharged circuit; SDC cell design; VLSI; alpha-particle injection; alpha-particle-induced noise suppression; arithmetic and logic unit; cell-based design methodology; design methodology; high-speed arithmetic modules; high-speed modules; low-voltage operation; macrocells; mainframe execution unit; parallel adder; precharged circuit technology; shielded dynamic complex-gate; ultrafast operation; Arithmetic; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit noise; Clocks; Design methodology; Laboratories; Macrocell networks; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
