A multiprocessor-based digital speech compressor

The hardware design of a digital speech compressor based on linear predictive coding is considered. In contrast to existing, high-speed single CPU implementations, a multiprocessor-based organization is proposed which could provide synthetic quality speech in a smaller package and at a lower cost. Currently available microprocessors are examined and two possible candidates, the Intel 2920 and the AMI S2811, are identified. Simulation tests of the resulting hardware indicate that severe degradation in the synthesized speech can be caused by the internal organizations of these special microprocessors. A composite processor resembling the 2920 is proposed, which yields adequate performance and makes the described multiprocessor-based architecture viable.