• DocumentCode
    1323103
  • Title

    Design for test technique for increasing the resolution of supply current monitoring in analogue circuits

  • Author

    Chalk, C.D. ; Zwolinski, M.

  • Author_Institution
    Dept. of Electron. & Comput. Sci., Southampton Univ., UK
  • Volume
    33
  • Issue
    21
  • fYear
    1997
  • fDate
    10/9/1997 12:00:00 AM
  • Firstpage
    1746
  • Lastpage
    1748
  • Abstract
    A design-for-test (DFT) technique for analogue circuits is proposed which splits all high current transistors into two. This technique reduces the fault-masking effects of the fault-free parts of the circuit, giving a potential fault cover of over 99%. Other advantages are the small area overhead and a low performance penalty
  • Keywords
    analogue integrated circuits; design for testability; integrated circuit design; integrated circuit testing; monitoring; DFT technique; analogue circuits; design-for-test technique; fault coverage; resolution; supply current monitoring;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19971174
  • Filename
    633366
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1323103