• DocumentCode
    1323695
  • Title

    Hole Mobility Characteristics in Si Nanowire pMOSFETs on (110) Silicon-on-Insulator

  • Author

    Chen, Jiezhi ; Saraya, Takuya ; Hiramoto, Toshiro

  • Volume
    31
  • Issue
    11
  • fYear
    2010
  • Firstpage
    1181
  • Lastpage
    1183
  • Abstract
    In this letter, hole mobility characteristics in Si gate-all-around nanowires on (110)-oriented silicon-on-insulator substrate have been studied, based on the advanced split C-V method. Fabricated nanowires have rectangular shape, and the height is fixed to 18 nm. High hole mobility in [110]-directed nanowires (widths ranging from 25 to 68 nm) were observed, illustrating 2.4 X enhancements over the universal (100) hole mobility in high Ninv region. Furthermore, effects of uniaxial stress in nanowires were investigated. It was found that [110]-directed nanowires were more sensitive to the applied stress in high Ninv region. Underlying physical mechanisms are also discussed.
  • Keywords
    MOSFET; hole mobility; nanowires; silicon-on-insulator; fabricated nanowires; hole mobility characteristics; pMOSFET; silicon-on-insulator; split C-V method; Degradation; Logic gates; MOSFETs; Nanoscale devices; Silicon; Stress; Substrates; (110) silicon-on-insulator (SOI); Gate-all-around (GAA) nanowire; Si; hole mobility; split $C$–$V$ method;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2010.2064154
  • Filename
    5570922
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1323695