DocumentCode :
1323999
Title :
Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes
Author :
Patil, Nishant ; Lin, Albert ; Zhang, Jie ; Wei, Hai ; Anderson, Kyle ; Wong, H. S Philip ; Mitra, Subhasish
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Volume :
10
Issue :
4
fYear :
2011
fDate :
7/1/2011 12:00:00 AM
Firstpage :
744
Lastpage :
750
Abstract :
We present a new very large scale integration (VLSI)-compatible metallic carbon nanotube (CNT) removal technique called VLSI-compatible metallic CNT removal (VMR) that overcomes challenges of existing techniques by combining design and processing to create carbon nanotube field effect transistors (CNFET) circuits immune to CNT imperfections such as metallic and mispositioned CNTs. Using VMR, we experimentally demonstrate combinational and sequential CNFET logic circuits such as half-adder sum generators and D-latches. These circuits form the fundamental building blocks of VLSI digital systems.
Keywords :
VLSI; carbon nanotubes; combinational circuits; field effect logic circuits; field effect transistor circuits; nanotube devices; sequential circuits; C; D-latches; VLSI-compatible metallic carbon nanotube removal technique; carbon nanotube field effect transistor circuits; combinational CNFET logic circuits; half-adder sum generators; mispositioned carbon nanotubes; sequential CNFET logic circuits; storage circuits; CNTFETs; Electric breakdown; Electrodes; Layout; Logic circuits; Logic gates; Metals; CNFET combinational and sequential circuits; Carbon nanotube field effect transistors (CNFETs); metallic carbon nanotubes (CNTs); very large scale integration (VLSI)-compatible metallic CNT removal;
fLanguage :
English
Journal_Title :
Nanotechnology, IEEE Transactions on
Publisher :
ieee
ISSN :
1536-125X
Type :
jour
DOI :
10.1109/TNANO.2010.2076323
Filename :
5570974
Link To Document :
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