DocumentCode :
1325175
Title :
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits
Author :
Jaberipur, Ghassem ; Parhami, Behrooz
Author_Institution :
Dept. of Electr. & Comput. Eng., Shahid Beheshti Univ., Tehran, Iran
Volume :
6
Issue :
5
fYear :
2012
fDate :
9/1/2012 12:00:00 AM
Firstpage :
259
Lastpage :
268
Abstract :
Most common uses of negatively weighted bits (negabits), normally assuming arithmetic value -1(0) for logical 1(0) state, are as the most significant bit of 2-s-complement numbers and negative component in binary signed-digit (BSD) representation. More recently, weighted bit-set (WBS) encoding of generalised digit sets and practice of inverted encoding of negabits (IEN) have allowed for easy handling of any equally weighted mix of negabits and ordinary bits (posibits) via standard arithmetic cells (e.g., half/full adders, compressors, and counters), which are highly optimised for a host of simple and composite figures of merit involving delay, power, and area, and are continually improving due to their wide applicability. In this paper, we aim to promote WBS and IEN as new design concepts for designers of computer arithmetic circuits. We provide a few relevant examples from previously designed logical circuits and redesigns of established circuits such as 2-s-complement multipliers and modified booth recoders. Furthermore, we present a modulo-(2n+1) multiplier, where partial products are represented in WBS with IEN. We show that by using standard reduction cells, partial products can be reduced to two. The result is then converted, in constant time, to BSD representation and, via simple addition, to final sum.
Keywords :
logic circuits; logic design; multiplying circuits; BSD; IEN; WBS; arithmetic algorithms; arithmetic value; binary signed digit; computer arithmetic circuits; inverted encoding of negabits; logical circuits; modulo-(2n+1) multiplier; negabits; negative component; negatively weighted bits; posibits; standard reduction cells; weighted bitset; weighted collection;
fLanguage :
English
Journal_Title :
Computers & Digital Techniques, IET
Publisher :
iet
ISSN :
1751-8601
Type :
jour
DOI :
10.1049/iet-cdt.2011.0059
Filename :
6336870
Link To Document :
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