DocumentCode
1325940
Title
Automatic router for the pin grid array package
Author
Chen, S.-S. ; Chen, J.-J. ; Tsai, C.-C. ; Chen, S.J.
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
146
Issue
6
fYear
1999
fDate
11/1/1999 12:00:00 AM
Firstpage
275
Lastpage
281
Abstract
A pin grid array (PGA) package router is described. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment, topological routing and geometrical routing. Examples tested on a Windows-based environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to manual routing, this router has a user-friendly graphic interface and can be applied practically to industrial strength VLSI packaging
Keywords
circuit layout CAD; integrated circuit layout; packaging; I/O pads; Windows-based environment; automatic router; chip cavity; geometrical routing; industrial strength VLSI packaging; layer assignment; pad-to-pin nets; pin grid array package router; planar interconnection; topological routing; user-friendly graphic interface;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings -
Publisher
iet
ISSN
1350-2387
Type
jour
DOI
10.1049/ip-cdt:19990797
Filename
838804
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