• DocumentCode
    1326554
  • Title

    Operational-amplifier compilation with performance optimization

  • Author

    Onodera, Hidetoshi ; Kanbara, Hiroyuki ; Tamaru, Keikichi

  • Author_Institution
    Dept. of Electron., Kyoto Univ., Japan
  • Volume
    25
  • Issue
    2
  • fYear
    1990
  • fDate
    4/1/1990 12:00:00 AM
  • Firstpage
    466
  • Lastpage
    473
  • Abstract
    A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density
  • Keywords
    CMOS integrated circuits; circuit CAD; circuit layout CAD; operational amplifiers; optimisation; CMOS operational-amplifier compiler; circuit performance; compact layouts; designing analog circuits; device sizing; layout CAD; layout density; layout design; layout parasitics; nonlinear optimization method; performance constraints; performance optimization; performance specifications; procedural layout technique; process parameters; simultaneous device sizing; single design process; topological design; Analog circuits; Circuit optimization; Circuit simulation; Circuit synthesis; Constraint optimization; Costs; Design methodology; Design optimization; Operational amplifiers; Process design;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.52171
  • Filename
    52171