DocumentCode
1326602
Title
Application of Enhanced Phase-Locked Loop System to the Computation of Synchrophasors
Author
Karimi-Ghartemani, Masoud ; Ooi, Boon-Teck ; Bakhshai, Alireza
Author_Institution
Dept. of Electr. & Comput. Eng., Queen´´s Univ., Kingston, ON, Canada
Volume
26
Issue
1
fYear
2011
Firstpage
22
Lastpage
32
Abstract
This paper introduces the application of an enhanced phase-locked loop (EPLL) system to the estimation of synchrophasors in a phasor measurement unit (PMU). The major concern is accurate estimation within off-nominal frequency operation of the system. The well-known technique based on discrete Fourier transform (DFT) can provide accurate estimation of the phasors in a three-phase balanced system. However, the negative-sequence component causes errors to the DFT estimates. The DFT cannot accomplish this task in a single-phase system. The EPLL is shown to be a solution for those shortcomings of the DFT technique, both in single-phase and in unbalanced three-phase systems, at the expense of some more complicated structure. Extensive steady-state and dynamic tests are performed and the results are presented and discussed.
Keywords
discrete Fourier transforms; phase locked loops; phase measurement; discrete Fourier transform; phase locked loop system; phasor measurement unit; synchrophasor estimation; unbalanced three phase systems; Discrete Fourier transforms; Frequency estimation; Phase locked loops; Phasor measurement units; Power systems; Steady-state; IEEE Std. C37.118-2005; enhanced phase-locked loop (EPLL); phasor measurement unit (PMU); synchrophasor; wide-area measurement systems (WAMS);
fLanguage
English
Journal_Title
Power Delivery, IEEE Transactions on
Publisher
ieee
ISSN
0885-8977
Type
jour
DOI
10.1109/TPWRD.2010.2064341
Filename
5575433
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