DocumentCode
1327150
Title
Accurate Compact Modeling for Sub-20-nm nand Flash Cell Array Simulation Using the PSP Model
Author
Jeon, Jongwook ; Park, Il Han ; Kang, Myounggon ; Hahn, Wookghee ; Choi, Kihwan ; Yun, Sunghee ; Yang, Gi-Young ; Lee, Keun-Ho ; Park, Young-Kwan ; Chung, Chilhee
Author_Institution
Semicond. R&D Center, Samsung Electron. Co., Ltd., Hwaseong, South Korea
Volume
59
Issue
12
fYear
2012
Firstpage
3503
Lastpage
3509
Abstract
In this paper, we have developed a new floating-gate-type Flash cell compact model based on the channel potential by using PSP metal-oxide-semiconductor description. Cell-to-cell coupling, Fowler-Nordheim tunneling, and new leakage current formulas have been implemented on Verilog-A compact model. The channel potential calculation of the PSP model enables accurate modeling of channel coupling and leakage currents which are associated with the boosted channel. In addition, the model parameter extraction procedure through 3-D technology computer-aided design (TCAD) and SPICE simulation is presented. The simulation results agree well with measured data of sub-20-nm nand cells.
Keywords
MOS memory circuits; NAND circuits; flash memories; floating point arithmetic; hardware description languages; leakage currents; 3D technology computer-aided design; Fowler-Nordheim tunneling; NAND flash cell array; PSP metal-oxide-semiconductor description; PSP model; SPICE simulation; TCAD; Verilog-A compact model; boosted channel; cell-to-cell coupling; channel coupling; channel potential calculation; floating-gate-type flash cell compact model; leakage current; parameter extraction; size 20 nm; Arrays; Capacitance; Computational modeling; Couplings; Flash memory; Leakage current; Tunneling; Cell-to-cell coupling; Fowler–Nordheim (FN) tunneling; SPICE simulation; compact modeling; leakage current; nand Flash;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2012.2219863
Filename
6339037
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