A self-aligned retrograde twin-well structure with buried p+ -layer

A self-aligned retrograde twin-well structure with a buried p⁺-layer surrounding the n-well is presented. The retrograde twin well and buried p⁺-layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions, and the channel stop processes are eliminated by using tight spatial distributions of retrograde n- and p-wells. This simple process is compatible with both local oxidation of silicon (LOCOS) and trench isolation processes and allows a scalable CMOS structure for very tight n⁺-to-p⁺ spacing. The present CMOS structure provides high latchup immunity at 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stop dopings