A partitioning scheme for optimizing interconnect power

Author

Mehra, Renu ; Guerra, Lisa M. ; Rabaey, Jan M.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

32

Issue

3

fYear

1997

fDate

3/1/1997 12:00:00 AM

Firstpage

433

Lastpage

443

Abstract

An architecture-synthesis technique for the low-power implementation of real-time applications is presented. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. This results in reduced usage of long high-capacitance buses, fewer accesses to multiplexors and buffers, and more compact layouts. Experimental results show average reductions in bus and multiplexor power of 57.8 and 56.0%, respectively, resulting in an average reduction of 25.8% in total power. In addition, we analyze the effect of varying levels of partitioning on power consumption and present models for estimating bus capacitance

Keywords

capacitance; circuit layout CAD; circuit optimisation; high level synthesis; integrated circuit interconnections; integrated circuit layout; logic partitioning; real-time systems; CAD; algorithm partitioning; architecture-synthesis technique; bus capacitance; compact layouts; digital design; interconnect power optimisation; long high-capacitance buses; low-power implementation; partitioning scheme; power consumption; real-time applications; Capacitance; Design automation; Electric breakdown; Energy consumption; Filters; Hardware; Integrated circuit interconnections; Integrated circuit synthesis; Multiprocessor interconnection networks; Partitioning algorithms;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.557644

Filename

557644