A 1.8-mW CMOS /spl Sigma//spl Delta/ modulator with integrated mixer for A/D conversion of IF signals

Author

Breems, Lucien J. ; Van Der Zwan, Eric J. ; Huijsing, Johan H.

Author_Institution

Delft Univ. of Technol., Netherlands

Volume

35

Issue

4

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

468

Lastpage

475

Abstract

In this paper, the design of a continuous-time baseband sigma-delta (/spl Sigma//spl Delta/) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF /spl Sigma//spl Delta/ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF /spl Sigma//spl Delta/ modulator is 0.2 mm/sup 2/ in 0.35-/spl mu/m CMOS.

Keywords

CMOS integrated circuits; cellular radio; intermodulation distortion; low-power electronics; sigma-delta modulation; signal sampling; 0.35 micron; 1.8 mW; 2.5 V; 200 kHz; A/D conversion; CMOS sigma-delta modulator; GSM channel; IF input tones; IF signals; dynamic range; integrated mixer; intermediate frequencies; power consumption; quadrature configuration; sampling rate; third-order intermodulation distortion; Analog-digital conversion; Baseband; Chirp modulation; Delta-sigma modulation; Digital modulation; Distortion measurement; Energy consumption; GSM; Mixers; Sampling methods;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.839907

Filename

839907