A low logic depth complex multiplier using distributed arithmetic

Author

Berkeman, Anders ; Öwall, Viktor ; Torkelson, Mats

Author_Institution

Dept. of Appl. Electron., Lund Univ., Sweden

Volume

35

Issue

4

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

656

Lastpage

659

Abstract

A combinatorial complex multiplier has been designed for use in a pipelined fast Fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input-to-output delay as short as possible. A new architecture based on distributed arithmetic, Wallace-trees, and carry-lookahead adders has been developed. The multiplier has been fabricated using standard cells in a 0.5-/spl mu/m process and verified for functionality, speed, and power consumption. Running at 40 MHz, a multiplier with input wordlengths of 16+16 times 10+10 bits consumes 54% less power compared to an distributed arithmetic array multiplier fabricated under equal conditions.

Keywords

CMOS logic circuits; carry logic; distributed arithmetic; integrated circuit design; logic design; multiplying circuits; pipeline arithmetic; 0.5 micron; 40 MHz; CMOS process; Wallace-trees; carry-lookahead adders; combinatorial complex multiplier; distributed arithmetic; fast Fourier transform processor; low logic depth complex multiplier; pipelined FFT processor; power consumption; Arithmetic; Clocks; Delay; Fast Fourier transforms; Logic arrays; Pipelines; Process design; Registers; Throughput; Wire;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.839928

Filename

839928