Title :
The XMOS Architecture and XS1 Chips
Author_Institution :
Comput. Sci. Dept., Bristol Univ., Bristol, UK
Abstract :
The XMOS architecture scales from real-time systems with a single multithreaded processor to systems with thousands of processors. Concurrent processing, communications, and I/O are supported by the instruction set of the XCORE processors and by the message-routing techniques and protocols in the XMOS interconnect. The event-driven architecture supports energy-efficient multicore and multichip systems in which cores are active only when needed.
Keywords :
concurrency control; multi-threading; multiprocessing systems; parallel architectures; XCORE processor; XMOS architecture; XMOS interconnect; XS1 chips; concurrent processing; energy-efficient multicore system; event-driven architecture; message-routing technique; multichip system; multithreaded processor; protocol; real-time system; Computer architecture; Instruction sets; Multithreading; Programming; Real-time systems; Registers; XCore processor; XMOS architecture; XMOS interconnect; energy efficiency; multichip; multicore; multithreaded processor;
Journal_Title :
Micro, IEEE
