Title :
VLSI implementation of a second-order digital filter
Author :
Sunder, Sanjay ; El-Guibaly, F. ; Antoniou, Athanasios
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
fDate :
7/1/1994 12:00:00 AM
Abstract :
The implementation of a second-order digital filter is discussed. A novel multiplier, by means of which an inner product operation is performed without the use of an accumulator, is used as a component in the second-order filter to achieve significantly reduced area and noise. In this multiplier, maximum use is made of all the cells comprising the multiplier.
Keywords :
VLSI; digital arithmetic; digital filters; multiplying circuits; VLSI; inner product operation; multiplier cells; novel multiplier; second-order digital filter; Adders; Delays; Digital filters; Limit-cycles; Logic gates; Quantization (signal); Registers;
Journal_Title :
Electrical and Computer Engineering, Canadian Journal of
DOI :
10.1109/CJECE.1994.6593846
