Algorithm for designing efficient VLSI concurrent add-multiply and add-multiply-add cells for DSP applications

A new algorithm is presented to (i) multiply two operands represented in hybrid notation, namely, one as a single vector and the other as two carry-save vectors of logic `1´s and `0´s, and (ii) to minimise and subsequently add the resulting sign extension bits concurrently with (i). The use of the proposed algorithm results in the complete elimination of the need for the separate adder modules normally used in conventional schemes for implementing add-multiply, add-multiply-add, add-multiply-add-multiply, dual-multiply operations frequently encountered in many DSP applications. Design examples are presented for illustrative purposes