Efficient algorithm for test vector decompression using an embedded processor

A new algorithm for implementing test vector compression in software is presented. It is based on a compression procedure recently invented by Melhem, et al., called RDIS (recursively defined invertible set) [Melham 12]. While RDIS was originally proposed for a memory correction application, it is shown here to be very well suited for the problem of compressing test vectors. When the inputs that are unassigned during ATPG are left as don´t cares (forming “test cubes”), typically only 1-2% of the remaining bits are care bits. It is shown that the RDIS procedure is very efficient when the number of care bits is small and is able to achieve large amounts of compression. The RDIS procedure works by recursively constructing invertible sets and efficiently encoding the information with row and column counts. The compressed data is stored on the tester. The tester then transfers this data to an embedded processor´s memory, and a simple decompression program is executed on the embedded processor which uses this information to reconstruct the original test cubes which can then be used for testing a chip, board, or system. Experimental results are shown which indicate that significant amounts of compression can be achieved independent of the dimensions of the test cube matrix.