Title :
Concentrator circuit with multiple priority levels
Author :
Krishnamoorthy, A.V. ; Lih-Yih Chiou ; Rozier, R.G. ; Kibar, O.
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
fDate :
3/16/2000 12:00:00 AM
Abstract :
The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 μm CMOS technology
Keywords :
CMOS digital integrated circuits; line concentrators; packet switching; 0.5 micron; 16-channel test chip; CMOS packet concentrator circuit; dynamic statistical multiplexing; memory-less packet concentrator architecture; multiple priority levels;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20000287
