DocumentCode
1330394
Title
Signed digit addition and related operations with threshold logic
Author
Cotofana, Sorin ; Vassiliadis, Stamatis
Author_Institution
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Volume
49
Issue
3
fYear
2000
fDate
3/1/2000 12:00:00 AM
Firstpage
193
Lastpage
207
Abstract
Assuming signed digit number representations, we investigate the implementation of some addition related operations assuming linear threshold networks. We measure the depth and size of the networks in terms of linear threshold gates. We show first that a depth-2 network with O(n) size, weight, and fan-in complexities can perform signed digit symmetric functions. Consequently, assuming radix-2 signed digit representation, we show that the two operand addition can be performed by a threshold network of depth-2 having O(n) size complexity and O(1) weight and fan-in complexities. Furthermore, we show that, assuming radix-(2n-1) signed digit representations, the multioperand addition can be computed by a depth-2 network with O(n3) size with the weight and fan-in complexities being polynomially bounded. Finally, we show that multiplication can be performed by a linear threshold network of depth-3 with the size of O(n3) requiring O(n3) weights and O(n2 log n) fan-in
Keywords
digital arithmetic; threshold logic; carry-free addition; depth-2 network; depth-3; fan-in; linear threshold network; linear threshold networks; multiplication; neural networks; radix-2 signed digit representation; redundant adders; redundant multipliers; signed digit number representations; signed-digit arithmetic; signed-digit number representation; threshold gates; threshold logic; Boolean functions; CMOS logic circuits; CMOS technology; Computer networks; Digital arithmetic; Impedance; Logic devices; Neural networks; Polynomials; Size measurement;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.841124
Filename
841124
Link To Document