Design and implementation of a general-purpose median filter unit in CMOS VLSI

A general-purpose median filter unit configuration in the form of two single-chip median filters, one extensible and one real time, is described. The networks of the chips are pipelined and systolic at bit level and based on odd/even transposition sorting. The chips are implemented in 3-μm standard CMOS using full-custom VLSI design techniques. The exact median of elements, in a window size w=9 with arbitrary word length L, can be found using only one extensible median filter chip. The filter can be extended to arbitrary window size and word lengths by using many chips. Simulation results show that the extensible median filter chip can be clocked up to 40 MHz and can generate 30/L megamedians per second. The real-time median filter chip can find the exact running medians of elements in a window of a fixed size w=9 with L=8. Simulations show that it can generate up to 50 megamedians per second with a 50-MHz clock. The algorithms, VLSI implementations, and chip test results are presented, along with some possible applications