A self-off-time detector for reducing standby current of DRAM

A self-off-time detector is proposed for reducing the standby current due to various voltage generators in DRAM´s. It automatically evaluates an optimal off-time interval and controls the dynamic ON/OFF switching ratio of power-dissipation circuits such as level detectors. A substrate back-bias voltage generator based on the proposed self-off-time detector scheme has been implemented using a 0.35-μm double-poly double-metal CMOS process. Measured results show that the total average standby current in the substrate back-bias voltage generator, except for the pumping current component which eventually arises from the leakage current, is less than 0.2 μA over the leakage current range of 0.1-1 μA. This scheme can he directly applied to all of the voltage generators in DRAM´s as well as the self-refresh circuit without much modification