A self-off-time detector for reducing standby current of DRAM

Author

Song, Ho-Jun

Author_Institution

Dept. of Electron. Eng., Chungnam Nat. Univ., Taejon, South Korea

Volume

32

Issue

10

fYear

1997

fDate

10/1/1997 12:00:00 AM

Firstpage

1535

Lastpage

1542

Abstract

A self-off-time detector is proposed for reducing the standby current due to various voltage generators in DRAM´s. It automatically evaluates an optimal off-time interval and controls the dynamic ON/OFF switching ratio of power-dissipation circuits such as level detectors. A substrate back-bias voltage generator based on the proposed self-off-time detector scheme has been implemented using a 0.35-μm double-poly double-metal CMOS process. Measured results show that the total average standby current in the substrate back-bias voltage generator, except for the pumping current component which eventually arises from the leakage current, is less than 0.2 μA over the leakage current range of 0.1-1 μA. This scheme can he directly applied to all of the voltage generators in DRAM´s as well as the self-refresh circuit without much modification

Keywords

CMOS memory circuits; DRAM chips; integrated circuit measurement; leakage currents; pulse generators; 0.1 to 1 muA; 0.35 micron; DRAM; double-poly double-metal CMOS process; dynamic ON/OFF switching ratio; leakage current; level detectors; optimal off-time interval; power-dissipation circuits; self-off-time detector; self-refresh circuit; standby current; substrate back-bias voltage generator; total average standby current; voltage generators; Automatic control; CMOS process; Current measurement; Detectors; Leakage current; Optimal control; Random access memory; Standby generators; Switching circuits; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.634661

Filename

634661