DocumentCode
1330519
Title
A detailed analysis of CMOS SRAM´s with gate oxide short defects
Author
Segura, Jaume ; Rubio, Antonio
Author_Institution
Dept. of Phys., Balearic Islands Univ., Palma de Mallorca, Spain
Volume
32
Issue
10
fYear
1997
fDate
10/1/1997 12:00:00 AM
Firstpage
1543
Lastpage
1550
Abstract
Using a model of gate oxide short defects, previously developed and validated experimentally, we investigate the behavior of CMOS SRAM memories having this defect. Faulty behaviors caused by gate oxide shorts are characterized classifying those that may cause a logic malfunction and those that degrade the memory operation without causing a logic error. Merits of SRAM test algorithms to detect gate oxide shorts are analyzed, identifying which are effective in terms of coverage and test cost
Keywords
CMOS memory circuits; SRAM chips; fault diagnosis; CMOS SRAM memory; gate oxide short defect; logic error; test algorithm; CMOS logic circuits; Circuit faults; Circuit testing; Degradation; Logic circuits; Logic devices; Logic testing; MOSFETs; Random access memory; Read-write memory;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.634662
Filename
634662
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