• DocumentCode
    1330532
  • Title

    Concurrent error detection and correction in a polynomial basis multiplier over GF(2m)

  • Author

    Huang, W.-T. ; Chang, C. Hwa ; Chiou, Che Wun ; Chou, F.H.

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Minghsin Univ. of Sci. & Technol., Hsinchu, Taiwan
  • Volume
    4
  • Issue
    3
  • fYear
    2010
  • fDate
    9/1/2010 12:00:00 AM
  • Firstpage
    111
  • Lastpage
    124
  • Abstract
    Finite-field arithmetic has been widely used to speed up the encryption and decryption processes in many cryptosystems, especially elliptic curve cryptosystems. Regular finite-field arithmetic structures are suitable for very large-scale integration implementation of cryptosystems, making them attractive for mobile commerce applications. Multiplication is the critical operation in finite-field arithmetic operations. Fault-based cryptanalysis is a new cryptanalysis method that deliberately injects faults into cryptographic devices, and requires only a small amount of side-channel information to break common ciphers. Thus, effective and simple methods for protecting the encryption/decryption circuitry from attackers are required to ensure that cryptographic devices can produce accurate signatures. This study presents a polynomial basis (PB) multiplier over GF(2m) with concurrent error detection (CED), and proposes a PB multiplier with concurrent error correction (CEC). A parallel structure of function cells is used in the proposed multiplier array to reduce the propagation delay. The proposed PB multiplier with internal parallel structure can reduce the time complexity by 28%, and reduce the space complexity by 90%, compared with existing PB multipliers. Compared with existing PB multipliers with CED, the proposed device with CED has a 20% greater space complexity but a 30% less time complexity. To the author%s knowledge, there is no previous report of PB multipliers with CEC capability. The proposed PB multiplier with CEC capability has a space complexity of only about 10% more and requires five more clock cycles than the proposed device without CEC capability.
  • Keywords
    digital arithmetic; polynomials; public key cryptography; concurrent error correction; concurrent error detection; cryptographic devices; decryption process; elliptic curve cryptosystems; encryption process; fault-based cryptanalysis; finite-field arithmetic; function cell parallel structure; mobile commerce applications; polynomial basis multiplier; side-channel information;
  • fLanguage
    English
  • Journal_Title
    Information Security, IET
  • Publisher
    iet
  • ISSN
    1751-8709
  • Type

    jour

  • DOI
    10.1049/iet-ifs.2009.0160
  • Filename
    5581824