A built-in self-test algorithm for row/column pattern sensitive faults in RAMs

Author

Franklin, Manoj ; Saluja, Kewal K. ; Kinoshita, Kozo

Author_Institution

Wisconsin Univ., Madison, WI, USA

Volume

25

Issue

2

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

514

Lastpage

524

Abstract

Row and column sensitive faults in RAMs are a class of faults in which the contents of a cell become sensitive to the contents of the row and column containing the cell in presence of a fault. A fault model that includes such faults is formally defined, and an algorithm to detect faults on the basis of this model is presented. Two different implementations of the algorithm for a VLSI built-in-self-test (BIST) environment are presented. They are a random-logic-based design and a microcode-based design. Additional properties of the algorithm, such as its capability to detect stuck-at faults, coupling faults, and conventional pattern sensitive faults, are identified

Keywords

VLSI; automatic testing; fault location; integrated circuit testing; integrated memory circuits; random-access storage; RAMs; VLSI BIST environment; built-in self-test algorithm; coupling faults; fault model; memory circuit testing; microcode-based design; random-logic-based design; row/column pattern sensitive faults; stuck-at faults; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Fault diagnosis; Helium; Logic testing; Random access memory; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.52179

Filename

52179