A strategy for modeling of variations due to grain size in polycrystalline thin-film transistors

Author

Wang, Albert W. ; Saraswat, Krishna C.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

47

Issue

5

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

1035

Lastpage

1043

Abstract

A strategy is presented for modeling of performance variation in polycrystalline thin-film transistors (TFT´s) due to grain size variation. A Poisson area scatter is used to model the number of grains in a TFT, which is converted to grain size and substituted into physically based models for threshold and mobility. An increase in device variation is predicted as the device and grain sizes converge through scaling or process changes. Comparison of the model with measurements of NMOS TFT´s results in reasonable agreement

Keywords

carrier mobility; elemental semiconductors; grain size; liquid crystal displays; semiconductor device models; silicon; thin film transistors; Poisson area scatter; Si; device variation; grain size; mobility; performance variation; physically based models; polycrystalline thin-film transistors; scaling; threshold; Active matrix liquid crystal displays; Grain size; Liquid crystal displays; MOS devices; Manufacturing processes; Random access memory; Semiconductor devices; Semiconductor process modeling; Silicon; Thin film transistors;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.841238

Filename

841238