Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus

Author

Namekawa, Toshimasa ; Miyano, Shinji ; Fukuda, Ryo ; Haga, Ryo ; Wada, Osamu ; Banba, Hironori ; Takeda, Satoru ; Suda, Kazuhiro ; Mimoto, Kenichiro ; Yamaguchi, Satoshi ; Ohkubo, Tsutomu ; Takato, Hiroshi ; Numata, Kenji

Author_Institution

Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

Volume

35

Issue

5

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

705

Lastpage

712

Abstract

A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is presented. This redundancy reduces the area required for spare cells from 6 to 1.6% of the area required for normal cells and improves chip yield from 50 to 80%. In addition, it provides a high-speed data path. An embedded DRAM macro adopting the redundancy achieves 200-MHz operation and provides 51.2-Gbit/s bandwidth. It has been fabricated with 0.25-/spl mu/m technology.

Keywords

DRAM chips; cellular arrays; integrated circuit design; integrated circuit yield; redundancy; 0.25 micron; 200 MHz; bandwidth; chip yield; dynamically shift-switched dataline redundancy; embedded DRAM macro; high-speed data path; wide data bus; Application software; Bandwidth; Clocks; Computer peripherals; Degradation; Logic; Microelectronics; Pins; Random access memory; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.841497

Filename

841497