Title :
Planarised interconnection technology using a new pillar formation method with multistacked metal structure
Author :
Park, M. ; Kim, G.H. ; Jang, J. ; Koo, J.G. ; Nam, K.S.
fDate :
8/29/1996 12:00:00 AM
Abstract :
A multilevel interconnection technology using both a new pillar structure consisting of multi-stacked metal layers and chemical-mechanical polishing planarisation has been proposed. This has several advantages such as self-aligned interconnection and decreased via-pillar resistance. The via-pillar resistance becomes one third of conventional via. In addition this method can improve the planarisation capability of inter-metal dielectrics
Keywords :
ULSI; electric resistance; integrated circuit interconnections; integrated circuit metallisation; polishing; ULSI; chemical-mechanical polishing; inter-metal dielectrics; multilevel interconnection technology; multistacked metal structure; pillar formation method; planarisation capability; planarised interconnection technology; self-aligned interconnection; via-pillar resistance;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961143