DocumentCode
1332123
Title
Planarised interconnection technology using a new pillar formation method with multistacked metal structure
Author
Park, M. ; Kim, G.H. ; Jang, J. ; Koo, J.G. ; Nam, K.S.
Volume
32
Issue
18
fYear
1996
fDate
8/29/1996 12:00:00 AM
Firstpage
1731
Abstract
A multilevel interconnection technology using both a new pillar structure consisting of multi-stacked metal layers and chemical-mechanical polishing planarisation has been proposed. This has several advantages such as self-aligned interconnection and decreased via-pillar resistance. The via-pillar resistance becomes one third of conventional via. In addition this method can improve the planarisation capability of inter-metal dielectrics
Keywords
ULSI; electric resistance; integrated circuit interconnections; integrated circuit metallisation; polishing; ULSI; chemical-mechanical polishing; inter-metal dielectrics; multilevel interconnection technology; multistacked metal structure; pillar formation method; planarisation capability; planarised interconnection technology; self-aligned interconnection; via-pillar resistance;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19961143
Filename
533415
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