Title :
A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization
Author :
Xanthopoulos, Thucydides ; Chandrakasan, Anantha P.
Author_Institution :
MIT, Cambridge, MA, USA
fDate :
5/1/2000 12:00:00 AM
Abstract :
This work describes the implementation of a discrete cosine transform (DCT) core compression system targetted to low-power video (MPEG2 MP@ML) and still-image (JPEG) applications. It exhibits two innovative techniques for arithmetic operation reduction in the DCT computation context along with standard voltage scaling techniques such as pipelining and parallelism. The first method dynamically minimizes the bitwidth of arithmetic operations in the presence of data spatial correlation. The second method trades off power dissipation and image compression quality (arithmetic precision). The chip dissipates 4.38 mW at 14 MHz and 1.56 V.
Keywords :
CMOS digital integrated circuits; VLSI; data compression; digital signal processing chips; discrete cosine transforms; distributed arithmetic; image coding; low-power electronics; parallel architectures; pipeline processing; video coding; 1.56 V; 14 MHz; 4.38 mW; CMOS process; DCT core compression system; JPEG applications; MP@ML; MPEG2; VLSI chip; adaptive bitwidth; arithmetic activity; arithmetic operation reduction; arithmetic precision; data spatial correlation; discrete cosine transform core; image compression quality; low-power DCT core; parallelism; pipelining; power dissipation; signal correlations; signal quantization; standard voltage scaling techniques; still-image applications; Arithmetic; Concurrent computing; Discrete cosine transforms; Image coding; Parallel processing; Pipeline processing; Power dissipation; Transform coding; Video compression; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
