A 5-GHz CMOS wireless LAN receiver front end

Author

Samavati, Hirad ; Rategh, Hamid R. ; Lee, Thomas H.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

35

Issue

5

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

765

Lastpage

772

Abstract

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-/spl mu/m CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm.

Keywords

CMOS analogue integrated circuits; MMIC amplifiers; MMIC mixers; circuit tuning; field effect MMIC; integrated circuit noise; microwave links; radio receivers; wireless LAN; 0.24 micron; 12.4 mW; 4.8 dB; 5 GHz; 5.2 dB; CMOS receiver front end; HIPERLAN; LNA; LNA/filter combination; SHF; automatically tuned third-order filter; low-noise amplifier; low-power PLL; mixers; noise reduction; phase-locked loop; wireless LAN receiver; CMOS technology; Circuits; FCC; Filters; Frequency; Low-noise amplifiers; Noise figure; Radio spectrum management; Signal to noise ratio; Wireless LAN;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.841505

Filename

841505