Title :
Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs
Author :
Li, Katherine Shu-Min ; Liao, Yi-Yu
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
An interconnect-driven layout-aware multiple scan tree (MST) synthesis methodology for 3-D integrated circuits (ICs) is proposed. MSTs, also known as scan forest, greatly reduce test data volume and test application time in system-on-a-chip testing. Previous studies on layout-aware scan tree synthesis only address 2-D layouts, so they cannot be directly applied to 3-D ICs. The proposed algorithm effectively optimizes both test compression rate and routing length under 3-D IC-induced constraints, and produces better results than all previous known methods.
Keywords :
integrated circuit interconnections; integrated circuit layout; integrated circuit testing; system-on-chip; three-dimensional integrated circuits; 2D layouts; 3D SoC; 3D integrated circuits; interconnect-driven methodology; layout-aware multiple scan tree synthesis; routing length; scan forest; system-on-a-chip testing; test application time; test compression rate; test data volume; Design for testability; System-on-a-chip; Test data compression; Three-dimensional integrated circuits; Design for testability; layout; multiple scan tree; routing; test data compression;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2012.2208644
