DocumentCode :
1332247
Title :
On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging
Author :
Lak, Zahra ; Nicolici, Nicola
Author_Institution :
Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, ON, Canada
Volume :
31
Issue :
12
fYear :
2012
Firstpage :
1845
Lastpage :
1856
Abstract :
Lifetime performance of digital integrated circuits degrades as a consequence of circuit aging. In the past few years, there has been extensive research to reduce the impact of aging by different design techniques, or to predict the degradation and adapt the circuit accordingly. In this paper, we explore a novel perspective to this problem by exploiting the presence of clock tuning elements in high-performance designs. By combining on-chip sensors to predict setup or hold-time violations with the clock tuning elements, we provide an effective self-tuning mechanism for each circuit sample. The proposed method can operate in-system to prolong the circuit´s maximum performance in its unique operating environment.
Keywords :
ageing; circuit tuning; clocks; delays; digital integrated circuits; integrated circuit design; circuit aging; clock configuration; delay degradation; digital integrated circuits; high performance designs; hold time violations; lifetime performance; on-chip clock tuning elements; on-chip sensors; self tuning mechanism; Aging; Degradation; Digital integrated circuits; Circuit aging; on-the-fly clock configuration; post-silicon clock tuning;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2012.2209883
Filename :
6349436
Link To Document :
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