Title :
VLSI design of optimization and image processing cellular neural networks
Author :
Chou, Eric Y. ; Sheu, Bing J. ; Chang, Robert C.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fDate :
1/1/1997 12:00:00 AM
Abstract :
Detailed design of a current-mode cellular neural network for optimization and image processing is presented. The hardware annealing function is also embedded in the network. It is a paralleled version of fast mean-field annealing in analog networks, and is highly efficient in finding globally optimal solutions for cellular neural networks. The network was designed to perform programmable functions for fine-grained processing with annealing control to enhance the output quality. A 5×5 prototype chip was fabricated in a 2.0 μm CMOS technology. Since the MOSIS scalable design rules are used, it is also suitable for submicron technologies. For high circuit reliability and compactness purpose, a unit current of 6.0 μA is used. The cell density is 505 cell/cm2 and the cell time constant is chosen to be 0.3 μs. From this prototype, a scalable VLSI core of around 50×50 neural processors can be integrated on a 1-cm2 silicon area in a 0.8 μm technology. Experimental results of building blocks and the prototype chip are also presented
Keywords :
CMOS integrated circuits; VLSI; cellular neural nets; image processing; integrated circuit design; neural chips; optimisation; simulated annealing; CMOS chip; MOSIS; VLSI design; current-mode cellular neural network; hardware annealing; image processing; optimization; programmable functions; submicron technology; Annealing; CMOS technology; Cellular neural networks; Circuits; Design optimization; Image processing; Neural network hardware; Process control; Prototypes; Very large scale integration;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
