DocumentCode :
1332632
Title :
N-Channel Dual-Workfunction-Gate MOSFET for Analog Circuit Applications
Author :
Na, Kee-Yeol ; Baek, Ki-Ju ; Kim, Yeong-Seuk
Author_Institution :
Chungbuk Provincial Coll., Okcheon, South Korea
Volume :
59
Issue :
12
fYear :
2012
Firstpage :
3273
Lastpage :
3279
Abstract :
Analog behaviors of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with dual-workfunction-gate (DWFG) structure are presented. The gate of the n-channel DWFG MOSFET is composed of p+ and n+ poly-Si along the channel carrier flowing direction. To investigate the impact of the proportional length of p- and n-type-doped poly-Si on analog behaviors, they are varied within a total physical gate length of 1.0 μm. Various dc characteristics that directly affect analog circuit performances are evaluated from the fabricated devices: I-V characteristics, drain-induced barrier lowering, transconductance (gm), drain conductance (gds = 1/rout), intrinsic gain (AV = gm/gds), and Early voltage (VEA = ID/gds). From the measurements, the DWFG devices always show improved characteristics over conventional devices (n+-doped poly-Si gate). The DWFG device with the shortest p+ poly-Si gate length (p/n = 0.4/0.6) shows better gm characteristics than other DWFG devices. The gds characteristics of the fabricated DWFG devices are improved as the length of the p+ poly-Si increases. The best AV and VEA are taken from the device with a p-type-doped poly-Si length of 0.7 μm (p/n = 0.7/0.3).
Keywords :
MOSFET; analogue integrated circuits; elemental semiconductors; semiconductor doping; silicon; work function; I-V characteristics; analog circuit; channel carrier; dc characteristics; drain conductance; drain-induced barrier lowering; dual-workfunction-gate structure; intrinsic gain; metal-oxide-semiconductor field-effect transistors; n-channel dual-workfunction-gate MOSFET; n-type-doped poly-Si; p-type-doped poly-Si; poly-silicon; proportional length; transconductance; Analog circuits; Electric potential; Ion implantation; Junctions; Logic gates; MOSFET circuits; Performance evaluation; Analog circuit; Early voltage $(V_{rm EA})$; channel length modulation (CLM); drain conductance $(g_{rm ds})$; drain-induced barrier lowering (DIBL); dual workfunction gate (DWFG); intrinsic gain $(A_{V})$; transconductance $(g_{m})$;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2012.2219865
Filename :
6352883
Link To Document :
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