• DocumentCode
    1332690
  • Title

    Implementation of signal power estimation methods

  • Author

    Cheng, Sei-Yeu ; Evans, Joseph B.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Kansas Univ., Lawrence, KS, USA
  • Volume
    44
  • Issue
    3
  • fYear
    1997
  • fDate
    3/1/1997 12:00:00 AM
  • Firstpage
    240
  • Lastpage
    250
  • Abstract
    Estimates of signal power are widely used in signal processing algorithms, particularly in adaptive algorithms. For example, normalized gradient search adaptive algorithms based on both transversal and lattice forms use an estimate of the signal power in order to provide robustness to the input signal environment. A limitation on the use of such methods is the complexity of traditional implementation strategies. In this paper, methods for performing sum-of-squares signal power estimation which may be implemented in an extremely simple manner are presented. These strategies are shown to provide excellent estimates with substantial implementation savings. Comparisons and example designs based on FPGAs and custom implementations illustrate the advantages of the new methods
  • Keywords
    CMOS digital integrated circuits; adaptive signal processing; digital arithmetic; digital signal processing chips; estimation theory; field programmable gate arrays; FPGA implementation; adaptive algorithms; custom implementations; signal power estimation methods; signal processing algorithms; sum-of-squares estimation; Adaptive algorithm; Adaptive signal processing; Hardware; Lattices; Least squares approximation; Logic; Robustness; Signal processing; Signal processing algorithms; Veins;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/82.558458
  • Filename
    558458