• DocumentCode
    1333061
  • Title

    Improved LOCOS isolation for thin-film SOI MOSFETs

  • Author

    Colinge, J.P. ; Crahay, A. ; de Ceuster, D. ; Dessard, V. ; Gentinne, B.

  • Author_Institution
    Microelectron. Lab., Univ. Catholique de Louvain, Belgium
  • Volume
    32
  • Issue
    19
  • fYear
    1996
  • fDate
    9/12/1996 12:00:00 AM
  • Firstpage
    1834
  • Lastpage
    1835
  • Abstract
    The authors propose the use of a recessed LOCOS technique instead of a standard LOCOS process to eliminate parasitic edge transistor leakage in thin-film SOI MOSFETs. This technique helps to increase the sidewall threshold voltage by both avoiding excess boron segregation into the field oxide, and providing a smoother edge rounding than that obtained by a classical LOCOS process
  • Keywords
    MOSFET; isolation technology; leakage currents; segregation; silicon-on-insulator; LOCOS isolation; Si; edge rounding; parasitic edge transistor leakage; recessed LOCOS technique; segregation; sidewall threshold voltage; thin-film SOI MOSFETs;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19961210
  • Filename
    533615
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1333061