Investigation on maximal throughput of a CMOS repeater chain

Author

Larsson-Edefors, Per

Author_Institution

Dept. of Phys., Linkoping Univ., Sweden

Volume

47

Issue

4

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

602

Lastpage

606

Abstract

This paper investigates the performance of a simple repeater chain interconnection for high-speed on-chip data transfer. The data in the repeater chain is distributed over a number of identical inverters, which are optimized with respect to size and position along the chain. It is shown how the distributed interconnection compares, in terms of throughput and power consumption, with a lumped driver consisting of several cascaded inverters with a stage ratio larger than one. The performance of the repeater chain has been demonstrated by design and measurement of a 0.8-μm twin-well double-metal single-poly CMOS chip, in which a 4-mm repeater chain had a maximal data rate of 1.7 Gb/s at V _dd=5 V

Keywords

CMOS digital integrated circuits; high-speed integrated circuits; integrated circuit interconnections; 0.8 micron; 1.7 Gbit/s; 4 mm; 5 V; CMOS chip; CMOS repeater chain; distributed interconnection; double-metal single-poly CMOS process; high-speed onchip data transfer; inverters; maximal throughput; power consumption; repeater chain interconnection; twin-well CMOS process; Clocks; Energy consumption; Integrated circuit interconnections; Inverters; Microelectronics; Propagation delay; Repeaters; Semiconductor device measurement; Throughput; Transmitters;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.841866

Filename

841866