A review of 3-D packaging technology

Author

Al-Sarawi, Said F. ; Abbott, Derek ; Franzon, Paul D.

Author_Institution

Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia

Volume

21

Issue

1

fYear

1998

fDate

2/1/1998 12:00:00 AM

Firstpage

2

Lastpage

14

Abstract

This paper reviews the state-of-the-art in three-dimensional (3-D) packaging technology for very large scale integration (VLSI). A number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems. Vertical interconnect techniques are reviewed in detail. Technical issues such as silicon efficiency, complexity, thermal management, interconnection density, speed, power etc. are critical in the choice of 3-D stacking technology, depending on the target application, and are briefly discussed

Keywords

VLSI; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; multichip modules; 3D packaging technology; MCM stacking technologies; VLSI; bare dice stacking; complexity; interconnection density; portable systems; power; power consumption; silicon efficiency; speed; thermal management; vertical interconnect techniques; weight; Energy consumption; Energy management; Multichip modules; Packaging; Power system interconnection; Silicon; Stacking; Technology management; Thermal management; Very large scale integration;

fLanguage

English

Journal_Title

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1070-9894

Type

jour

DOI

10.1109/96.659500

Filename

659500