Architectures for the implementation of a fixed delay tree search detector

This paper examines the tradeoff between fixed delay tree search (FDTS) detector complexity and performance with various modulation codes. Several architectures suitable for implementing FDTS or achieving performance comparable to FDTS are presented. Recursive forms are derived by decomposing the branch metric computation while breaking down the entire path metric yields nonrecursive forms. The final architecture casts the detection problem into a signal space context in which the observation space is partitioned into decision regions. These structures are presented and evaluated in the context of an analog very large scale integration (VLSI) implementation. Compared to a direct mapping to hardware of the original algorithm, these alternative schemes offer reduced power consumption and/or increased data rate