DocumentCode
1334777
Title
A 4 GHz Continuous-Time 
ADC With 70 dB DR and 
74 dBFS THD in 125 MHz BW
Author
Bolatkale, Muhammed ; Breems, Lucien J. ; Rutten, Robert ; Makinwa, Kofi A A
Author_Institution
NXP Semicond., Eindhoven, Netherlands
Volume
46
Issue
12
fYear
2011
Firstpage
2857
Lastpage
2868
Abstract
A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer´s latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm2 including the modulator, clock circuitry and decimation filter.
Keywords
CMOS integrated circuits; analogue-digital conversion; delta-sigma modulation; harmonic distortion; radiofrequency filters; LP CMOS process; THD; bandwidth 125 MHz; clock circuitry; decimation filter; excess delay compensation; frequency 4 GHz; loop filter topology; modulator; power 260 mW; quantizer latency; size 45 nm; third-order continuous-time ΔΣ ADC; voltage 1.1 V; voltage 1.8 V; word length 4 bit; AC-DC power converters; Bandwidth allocation; CMOS integrated circuits; Frequency modulation; Wireless communication; Analog-to-digital conversion; CMOS analog integrated circuits; base stations; continuous-time filters; continuous-time sigma-delta modulation; delta-sigma modulator; multi-bit; oversampling ADCs; radio receivers; wireless communication;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2011.2164963
Filename
6029947
Link To Document