Title :
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals
Author :
Zhang, Ling ; Zhang, Yulei ; Chen, Hongyu ; Yao, Bo ; Hamilton, Kevin ; Cheng, Chung-Kuan
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, La lolla, CA, USA
fDate :
3/1/2011 12:00:00 AM
Abstract :
As semiconductor process technology scales down, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate, and compare various metrics with optimized wire configurations in the contexts of different design criteria: delay minimization, delay-power minimization, and delay2 -power minimization. We show how various design criteria influence the configuration, performance, and power consumption of repeated wires.
Keywords :
integrated circuit design; integrated circuit interconnections; wires (electric); delay-power minimization; design goals; energy metrics; interconnect planning; on-chip interconnect analysis; optimized wire configurations; power consumption; semiconductor process technology; Analysis; energy-delay optimization; high speed; interconnect; low power;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2009.2035322
