Title :
Efficient back-bias generator with cross-coupled hybrid pumping circuit for sub-1.5 V DRAMs
Author :
Min, Kyeotig-Sik
Author_Institution :
Memory Design Dept., Hyundai Microelectron. Co. Ltd., Cheongju, South Korea
fDate :
3/30/2000 12:00:00 AM
Abstract :
A very efficient back-bias generator with cross-coupled hybrid pumping circuit (CHPC) is presented. Though the CHPC is based on the previously suggested hybrid pumping circuit (HPC). Its cross-coupled nature which can totally eliminate the sacrificial voltage loss in storing the supply voltage (VCC) at the capacitor shows a much better pumping efficiency and increased pumping current over the HPC for VCC ranging from 3.3 to 0.9 V
Keywords :
DRAM chips; low-power electronics; 0.9 to 3.3 V; DRAMs; back-bias generator; cross-coupled hybrid pumping circuit; dynamic RAM; sacrificial voltage loss elimination;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20000485
