Performance analysis of an ATM MUX with a new space priority mechanism under ON-OFF arrival processes

We propose a new space priority mechanism, and analyze its performance in a single Constant Bit Rate (CBR) server. The arrival process is derived from the superposition of two types of traffics, each in turn results from the superposition of homogeneous ON-OFF sources that can be approximated by means of a two-state Markov Modulated Poisson Process (MMPP). The buffer mechanism enables the Asynchronous Transfer Mode (ATM) layer to adapt the quality of the cell transfer to the Quality of Service (QoS) requirements and to improve the utilization of network resources. This is achieved by “Selective-Delaying and Pushing-In” (SDPI) cells according to the class they belong to. The scheme is applicable to schedule delay-tolerant non-real time traffic and delay-sensitive real time traffic. Analytical expressions for various performance parameters and numerical results are obtained. Simulation results in term of cell loss probability conform with our numerical analysis.