DocumentCode :
1337321
Title :
Prolog to IDDQ testing for CMOS VLSI
Author :
Esch, Jim
Volume :
88
Issue :
4
fYear :
2000
fDate :
4/1/2000 12:00:00 AM
Firstpage :
542
Lastpage :
543
Keywords :
CMOS integrated circuits; CMOS technology; Circuit faults; Circuit testing; Costs; Current measurement; Integrated circuit measurements; Integrated circuit testing; Steady-state; Very large scale integration;
fLanguage :
English
Journal_Title :
Proceedings of the IEEE
Publisher :
ieee
ISSN :
0018-9219
Type :
jour
DOI :
10.1109/JPROC.2000.842999
Filename :
842999
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1337321
